BURIED WORDLINE PDF

BURIED WORDLINE PDF

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June 28, 2020

Before Qimonda’s unfortunate demise last year, they delivered an impressive paper at IEDM [1] describing a “buried wordline” (BwL). Memory chip supplier Qimonda says it is about to begin commercial production of DRAM chips using its new “Buried Wordline” technology. Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce.

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This application claims priority under 35 U. Example embodiments relate to a semiconductor device having a buried gate electrode and a method of fabricating the same. Recently, there has been increasing research on the buried word line cell array transistor BCAT in which a word line WL may be buried below the surface of a semiconductor substrate using a metal wordlnie not a polysilicon as a gate electrode in the structure of a conventional recess channel array transistor RCAT.

Unlike a polysilicon gate in a conventional DRAM, a word line having 0. A gate insulating layer 16 is disposed on the bottom surface and the inner surface of the trench A metal gate electrode 20which fills the trench 14 on the gate insulating layer 16 and protrudes beyond the substrate 10is formed. Spacers 24 are formed on both sides of the protruded metal gate electrode 20and a capping pattern 22 is disposed on the upper surface of metal gate electrode An active region of a source and drain is formed in the substrate adjacent to both sides of the metal gate electrode The metal gate electrode worsline can serve as a gate electrode and a word line.

6F2 buried wordline DRAM cell for 40nm and beyond

In the semiconductor device, the metal gate electrode 20 is buried into the substrate 10 and also protrudes beyond the surface of substrate, and accordingly, the spacer 24 for supporting the metal gate electrode 20 is required. Therefore, in the above structure, the semiconductor device having a height corresponding to the protruded portion of the metal gate electrode 20 is formed. Thus, the above structure is not ideal for embodying a thinner device.

For example, in order to secure a step coverage above However, chlorine ions in TiCl 4 are diffused into the oxide layers and silicon channels, thereby forming sordline in the oxide layers. As a result, reliability of the device is reduced.

6F2 buried wordline DRAM cell for 40nm and beyond – Semantic Scholar

The degradation of the oxide layers due to the occurrence of chlorine ions from applying the TiN layer, which is formed using a Bjried or an atomic layer deposition ALD method, is one of the causes of the problems described above.

Example embodiments provide a semiconductor device having a buried word line structure in which worcline gate electrode bjried a word wordine may be buried inside of a substrate, thereby reducing the height of the wkrdline device and the degradation of oxide layers due to the application of a TiN metal gate.

Example embodiments also provide a method of fabricating a semiconductor device having the buried word line structure as described above. According to example embodiments, a semiconductor device having a buried word line structure may comprise a semiconductor substrate wordkine by a device isolation layer and comprising an active region in which a trench for forming one or more recess channels are formed.

The semiconductor device having a buried word line structure may further comprise a gate insulating layer on the surface of the trench, a gate electrode layer on the surface of the gate insulating layer, and a buried word line burying the trench on the surface of the gate electrode layer. The top surface of the capping layer may be formed so as to not protrude beyond the surface of the substrate. The trench may have a width within a range of about 10 to about nm.

The gate electrode layer may have a thickness within a range of about 1 to about 10 nm. The buried word line may comprise any one selected from the group consisting of tungsten Waluminum Alcupper Cumolybdenum Motitanium Titantalum Taand ruthenium Ruor a combination thereof.

The buried word line may comprise a lower buried word line formed in the lower region of the gate electrode layer, and an upper buried word line formed in the upper region of the gate electrode layer. The upper buried word line may be formed of a material different from that of the lower buried word line.

The lower buried word line may comprise polysilicon. The upper buried word line may comprise a silicide. A method of fabricating a semiconductor device having a buried word line structure may comprise forming a device isolation layer defining an active region in a semiconductor substrate, forming a trench for forming one bried more recess channels in the active region, forming a gate insulating layer on the surface of the trench, forming a gate electrode layer on the surface of the gate insulating layer, and forming a buried word line burying the trench on the surface of the gate electrode layer.

The capping layer may be formed after forming wodline buried word line having the buried word line structure. The forming of the buried word line may comprise forming a word buired layer on the substrate so as to bury the trench, polishing the word line layer using chemical mechanical polishing CMP and an etch-back method which uses a qordline etch to expose the surface of the substrate, and recessing ubried polished word line layer into the substrate.

The gate electrode layer may be formed using a chemical vapor deposition CVD or an atomic layer deposition ALD method. The gate electrode layer may comprise polysilicon which may be formed using an atomic layer deposition method in which Si 3 H 8 may be used as a silicon wordkine gas.

The buried word line may be formed using a chemical vapor deposition, a physical vapor deposition PVD buriex, or an atomic layer deposition ALD method. The forming of the buried word line may comprise forming the lower buried word line in the lower region of the gate electrode layer, and forming the upper buried word line in the upper region of the gate electrode layer.

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The forming of the lower buried word line may comprise forming a first word line layer on the substrate so as to bury the trench, polishing the first word line layer using chemical mechanical polishing and an etch-back method which uses a dry etch to expose the surface of the substrate, and recessing the polished first word line layer into the substrate to form the lower buried word line. The forming of the upper buried word line may comprise forming a second word line layer on the substrate so as to bury the trench in which the lower buried word line is formed, polishing the second word line layer using chemical mechanical polishing and an etch back method which uses dry etch to expose the surface of the substrate, and recessing the polished second word line layer into the substrate to form the upper buried word line.

In example embodiments, a method of fabricating a semiconductor device having a buried word line structure may include forming a device isolation layer defining an active region in a semiconductor substrate, forming buuried trench for bured one or more recess channels in the active region, forming a gate insulating layer on a surface of the trench, forming a gate electrode layer on a surface wordpine the gate insulating layer, and forming a buried word line burying the trench on a surface of the gate electrode layer.

In example embodiments, forming of the buried word line may include forming a word line layer on the substrate so as to bury the trench, polishing the word line layer using chemical mechanical polishing CMP and an etch-back method which uses a dry etch to expose the surface of the substrate, and recessing the polished word line layer into the substrate.

In example embodiments, the gate electrode layer may be formed using a chemical vapor deposition CVD or an atomic layer deposition ALD method. In example embodiments, the gate electrode layer may include polysilicon which may be formed using the atomic layer deposition method in which Si 3 H 8 may be used as a silicon source gas.

In example embodiments, the buried word line may be formed using a chemical vapor deposition, a physical vapor deposition PVDor an atomic layer deposition ALD method.

In example embodiments, forming the buried word line may include forming a lower buried word line in a lower region of the gate electrode layer and forming an upper buried word line in an upper region of the gate electrode layer, the upper buried word line being formed of a material different from that of the lower buried word burisd.

In example embodiments, forming the worrline buried word line may include forming a first word line layer on the substrate so as to bury the trench, polishing the first word line layer using chemical mechanical polishing and an etch-back method which uses a dry etch to expose the surface of the substrate, and recessing the polished first word line layer into the substrate to form the lower buried word line.

In example embodiments, forming the upper buried word line may include forming a second word line layer on the substrate so as to bury the trench in which the lower buried word line may be formed, polishing the second word line layer using chemical mechanical polishing to expose the surface of the substrate, and recessing the polished second word line layer into the substrate to form the upper buried word line.

In example embodiments, the trench may burisd formed to have a width within a range of about worline to about nm.

‘Buried Wordline’ DRAM becomes reality | Electronics News

In example embodiments, the gate electrode layer may be formed to have a thickness within a range of about 1 to about 10 nm. In example embodiments, the buried word line may include any one selected from the group consisting of tungsten Waluminum Alcupper Cumolybdenum Motitanium Titantalum Taand ruthenium Ruor a combination thereof.

In example embodiments, the gate insulating layer may be a thermal oxide layer formed by thermal oxidation. Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Reference will now be made in detail to example embodiments, examples of which are illustrated in the accompanying drawings.

However, example embodiments are not limited to the embodiments illustrated hereinafter, and the embodiments herein are rather introduced to provide easy and complete understanding of the scope and spirit of example embodiments.

In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals refer to like elements throughout. It will be understood that, although the terms first, second, third etc. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.

It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented rotated 90 degrees or at other orientations and the spatially relative descriptors used herein interpreted accordingly.

‘Buried Wordline’ DRAM becomes reality

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of example embodiments and intermediate structures.

Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may be to include deviations in shapes that result, for example, from manufacturing. Woreline, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes may be not intended to illustrate the actual shape of a region of a device and wprdline not intended to limit the scope of example embodiments.

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Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The device isolation layer may be a shallow trench isolation STI for improving the speed and the degree of integration of the device, but is not limited thereto.

A trench forming a recess channel within the active region defined by the device isolation layer may be formed. The trench may be formed so as to have a width within a range of about 10 to about nm, for example, below 50 nm. One or more recess channels buuried be formed, and accordingly a plurality of trenches may be formed within the active woddline defined by the device isolation layer In order to form the trencha buffer insulating layer e.

Such technique is well known to those skilled in the art and thus, the detailed description thereof is omitted. In addition, a description of forming layers within and on the gate using deposition butied etching techniques is also well known to those skilled in the art, and thus, omitted. The gate insulating layer may be a thermal oxide layer formed by thermal oxidation.

The oxide layer formed on the top surface of the substrate when forming the gate insulating layer may be removed using a conventional method e. The gate electrode layer may be formed so as to have a thickness within a range of about 1 to about 10 nm, for example, below 5 nm.

Materials used to form the gate electrode layer will be described in detail below. The buried word line may be formed using a chemical vapor deposition, a physical vapor deposition PVDor an atomic layer deposition method. The top surfaces of the gate insulating layerthe gate aordline layerand the buried word line formed on the gate electrode layer may be formed so as to not protrude beyond the top surface of the substratee.

The buried word line may be formed by forming a word line layer on the substrate so as to bury the trench The word line layer may then be polished using a chemical mechanical polishing CMP method and etched back using a dry etch process to expose the surface of the substrate The buried word line may be formed by recessing the polished word line layer into the substrate using a partial etch process.

As illustrated, the gate electrode layer may be recessed to the same level as the buried word line However, this is merely illustrative and thus, the gate electrode layer and the buried word line are not limited to this recessed feature. Thus, the top surfaces of the gate electrode layer and the gate insulating layer may also be recessed within the substrate and may be formed such that the capping layer caps simultaneously the recessed regions of the gate insulating layer and the gate electrode layer and the recessed region of the buried word line The size of the recessed region of the gate insulating layerthe gate electrode layerand the buried word line may be equal to or maybe different from ubried other.

The capping layer may be formed of an insulating material e. Materials used to form the gate electrode layer and the buried word line will now be described in detail below. The gate electrode layer may be formed of polysilicon. In general, when thinly forming a polysilicon layer using an atomic layer deposition method, SiH 4 gas or Si 2 H 6 gas may be used as the silicon source gas.

However, when the width of the trench is less than about 50 nm, there may be a constraint that the thickness of the polysilicon layer be buriec more than about 5 nm. When using the atomic layer deposition method using SiH 4 gas or Si 2 H 6 gas, it may be more difficult to form a continuous layer having a thickness of about 5 nm. Therefore, wordlind order to form the continuous polysilicon layer having a width of about 5 nm, Si 3 H 8 gas may be used.

Accordingly, when the gate electrode layer includes polysilicon and is formed to a thickness of about 5 nm, the atomic layer deposition may be carried out using the Si 3 H 8 gas.

In example embodiments, the buried word line may be formed of any one selected from the group consisting of tungsten Waluminum Alcupper Cumolybdenum Motitanium Titantalum Taand ruthenium Ru buied, or a combination thereof. However, this is merely illustrative, and thus, the gate electrode layer and the buried word line are not limited to these materials. Hereinafter, the description overlapping with that described above will be omitted for the purpose of clarity.

The upper buried word line may be formed of a different material from that of the lower buried word line The lower buried word line may be formed by forming a first word line layer not shown on the substrate so as to bury the trench